Flip-flop equations excitation tables and registers
Predict a next state or design for it
A characteristic rule answers: given current state Q and input controls, what is Q_next? An excitation table asks the reverse: to obtain a required transition Q→Q_next, which controls may be used? Confusing these two directions is a common sequential-design error.
Prerequisites: edge-triggered storage, Boolean algebra and timing discipline. All flip-flops here sample at the same rising edge. Controls and old Q values satisfy setup/hold, reset is inactive unless stated, and Q_next means the state after the edge and settling. This is an ideal synchronous model, not a level-sensitive JK circuit. Gate-level race-around behavior and physical clock gating are not modeled.
D T and JK characteristic behavior
A D flip-flop copies its data: Q_next=D. A T flip-flop holds when T=0 and toggles when T=1, giving Q_next=Q⊕T. “Toggle” means complement the old Q, not force a 1.
For a JK flip-flop, J=K=0 holds, 01 resets, 10 sets and 11 toggles. The Boolean equation is Q_next=JQ′+K′Q. For Q=0 it reduces to J; for Q=1 it reduces to K′. Those two cases prove the table:
| J | K | Q_next |
|---|---|---|
| 0 | 0 | Q |
| 0 | 1 | 0 |
| 1 | 0 | 1 |
| 1 | 1 | Q′ |
Unlike an SR latch's forbidden simultaneous assertion, 11 is a valid toggle command in this edge-triggered JK model. Its functional rule does not imply that an arbitrary transparent JK implementation can toggle safely for a long clock level.
Worked example 1: Q starts at 0. Successive JK commands 10,00,11,01 produce states 1,1,0,0. At each step use the previous state, not the initial state. With T=1 continuously, a T flip-flop alternates 0,1,0,1,… at successive edges. One full output cycle spans two input periods, giving f_out=f_clock/2 in this ideal toggling regime.
Derive the excitation table
For D, the required input is always Q_next. For T, T=Q⊕Q_next: equal states need hold, unequal states need toggle. For JK, when old Q=0 only J determines Q_next, so K is irrelevant; when old Q=1 only K determines Q_next, so J is irrelevant.
| Q | Required Q_next | D | T | J | K |
|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | X |
| 0 | 1 | 1 | 1 | 1 | X |
| 1 | 0 | 0 | 1 | X | 1 |
| 1 | 1 | 1 | 0 | X | 0 |
X means either 0 or 1 is a valid design choice for that particular transition. It is not a physical unknown that must be driven into the chip. Once equations select a concrete choice, test that choice in the characteristic equation. Different choices can yield equivalent next-state behavior and different circuit costs.
For an active-high clocked SR element, valid transitions use: 0→0: S=0,R=X; 0→1: S=1,R=0; 1→0: S=0,R=1; 1→1: S=X,R=0. Keep S=R=1 forbidden. These excitation don't-cares permit only the listed choices; they do not authorize forbidden simultaneous controls.
Convert the required next-state function
Worked example 2: a state bit should toggle when input x=1 and hold when x=0. A T implementation uses T=x. A D implementation uses D=Q⊕x. A JK implementation can use J=K=x. Substituting into each characteristic rule produces the same Q_next, so the implementations agree for all four (Q,x) assignments.
Worked example 3: a D flip-flop should load external bit d only when enable e=1. Otherwise it must hold. Its data equation is D=e d+e′Q. This is a 2:1 MUX before the D input, selecting old Q or new d. The register still receives the regular clock; a Boolean enable does not require making a new clock by ANDing e with the clock. Uncontrolled clock gating can create unwanted edges and is outside this model.
A register updates all bits from the old state
An n-bit register is n storage bits with a common sampling event. For a parallel load, every D_i receives its corresponding input P_i and all bits update together. “Together” means one logical edge, not zero clock-to-Q delay or identical analog switching times.
Consider a four-bit shift register written Q_3Q_2Q_1Q_0. Define a right shift by D_3=s, D_2=Q_3, D_1=Q_2, D_0=Q_1, where s is the serial input. This explicit equation removes ambiguity about direction and entry point. The bit shifted out is the old Q_0.
Worked example 4: initial state 1011 and serial input 0 give next state 0101. A following edge with serial input 1 gives 1010. All right-hand Q bits refer to the state before that edge. Updating Q_3 and then using that newly changed value to compute Q_2 would describe a software-style in-place update, not these simultaneous flip-flops.
Combine load shift and hold with priority
Declare three choices: if L=1, parallel-load P; otherwise if E=1, shift with serial input s; otherwise hold. If L=E=1, load wins. For each bit, D_i=L P_i+L′(E shift_i+E′Q_i), where shift_i is the corresponding source defined above. This is a data-selection network feeding the register, not multiple competing writes.
Worked example 5: starting at 1011, L=0,E=1,s=0 produces 0101. Next L=0,E=0,s=1 holds 0101 because shifting is disabled. Next L=1,P=1100 loads 1100, regardless of E or s. If the reset rule is also present, its priority must be inserted explicitly before or after these choices as specified by the design.
Key points and mistakes
Characteristic equations predict; excitation tables design. X is controlled freedom, not an electrical level. D copies, T toggles conditionally and JK has four command cases. A register's next-state equations use old-state values consistently. State the bit order, shift direction, serial entry point and control priority. Check every transition, including holds and repeated commands; a few successful traces do not prove a general next-state equation.
Original practice
These six single-correct MCQs are original learning questions, not previous-year questions. Choose exactly one option.
C01. A T flip-flop has Q=1 and T=1 at a valid rising edge. What is Q_next?
A. 1 B. 0 C. Always unknown D. Equal to the clock level
Answer: B
A is incorrect: T=1 toggles rather than holds.
B is correct: 1⊕1=0.
C is incorrect: the valid synchronous contract defines the result.
D is incorrect: the clock triggers sampling; it is not the stored data.
C02. Which JK input requirement guarantees transition Q=0 to Q_next=1?
A. J=0,K=X B. J=X,K=1 C. J=1,K=X D. J=0,K=0
Answer: C
A is incorrect: with Q=0, Q_next equals J, so this keeps 0.
B is incorrect: J=0 is allowed by that X and would not set the state.
C is correct: at Q=0 the equation reduces to J, independent of K.
D is incorrect: 00 holds the existing 0.
C03. Which D input makes a D flip-flop toggle when x=1 and hold when x=0?
A. D=Q⊕x B. D=x C. D=Q+x D. D=Qx
Answer: A
A is correct: XOR with 0 preserves Q and XOR with 1 complements Q.
B is incorrect: it loads x rather than conditionally toggling old state.
C is incorrect: OR forces 1 when x=1 rather than toggling Q=1 to 0.
D is incorrect: AND forces 0 when x=0 rather than holding Q=1.
C04. For Q_3Q_2Q_1Q_0=1011 and right-shift equations D_3=s,D_2=Q_3,D_1=Q_2,D_0=Q_1, what is next state when s=0?
A. 0110 B. 0000 C. 1011 D. 0101
Answer: D
A is incorrect: this is a left shift with zero entering the low position.
B is incorrect: this can result from wrongly cascading new values through an in-place update.
C is incorrect: it holds rather than shifts.
D is correct: new bits are 0, old Q_3=1, old Q_2=0, old Q_1=1.
C05. A register gives parallel load L priority over shift E. With L=1,E=1 and P=0110, what is its next state?
A. The shifted old state B. The unchanged old state C. 0110 D. The bitwise OR of P and the shifted state
Answer: C
A is incorrect: shift is chosen only when L=0.
B is incorrect: holding applies when neither load nor shift is selected.
C is correct: load wins and copies P.
D is incorrect: priority selection chooses one source rather than combining competing results.
C06. In an excitation table, what does X mean?
A. The input must be physically metastable. B. Either Boolean value can satisfy this particular required transition. C. The output may be ignored even if its required value is specified. D. The input must alternate every cycle.
Answer: B
A is incorrect: X is a design choice, not an electrical requirement.
B is correct: choose a concrete 0 or 1 and verify the characteristic rule.
C is incorrect: the required transition must still be satisfied.
D is incorrect: no alternating behavior is implied.
Scope and sources
This is one bounded Digital Logic lesson, not complete GATE CS coverage. The official syllabus establishes relevance only; the derivations, examples and practice are original. Technical references were used to check representation and circuit conventions, not to reproduce their exercises.
Sources checked 14 October 2026.
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