Instruction execution and addressing modes
Learning objectives and boundaries
Follow a simple instruction through a processor, distinguish an address from the value stored there, calculate effective addresses, and count operand-memory reads. Prerequisites: basic arithmetic, variables and the idea of binary storage. These are architecture foundations, not complete coverage of processor design. Instruction encodings, control-unit design, interrupts, pipelines and virtual memory need separate lessons.
All examples use a deliberately specified teaching machine, not actual MIPS, x86 or RISC-V assembly. Memory is byte-addressed. Instructions and data words are four bytes long; every example access is aligned and valid. M[a] means the complete four-byte word beginning at byte address a, not the single byte there. R1 means a register name; R[R1] means its contents. We omit caches, exceptions and address translation. Values fit their registers, so arithmetic overflow is not involved.
1. From a program to processor state
An instruction set architecture (ISA) specifies the operations and programmer-visible behavior a machine supports. Its implementation decides how circuits carry them out. The same ISA need not imply the same number of cycles or physical stages.
A program counter (PC) identifies the next instruction to fetch in our teaching model. Fetch reads its instruction bits. Decode determines the operation and operand rules. Execution may calculate an address or perform arithmetic; a load or store accesses data memory; the result updates the specified register or memory location. A branch can replace the next PC instead of taking the ordinary sequential address.
These are logical activities, not a claim that every instruction uses five clock cycles. Some designs overlap activities; others take several cycles for one activity. Fetching an instruction and reading its data operand are distinct events.
For an instruction at byte address 100, the sequential successor in this model is 104 because the instruction is four bytes long. PC+1 would be correct only for a different stated addressing/length convention. A real ISA may define a branch's PC base differently, so a question must identify that base and displacement unit.
2. Address versus contents
Suppose M[500]=900 and M[900]=37. The number 500 is an address. Its stored word is 900, which can itself be interpreted as another address. Reading once obtains 900; following that pointer and reading again obtains 37. Do not silently replace an address with its contents.
For a memory operand, the effective address (EA) is where the operand is located after the addressing rule is applied. The operand is then M[EA]. Immediate and register operands do not require a data-memory EA. Here, logical operand-memory reads exclude instruction fetches, address translation and cache traffic.
3. A reusable addressing table
Let A be an address field, k an immediate constant, d a byte displacement and R a named register.
| Mode | Rule | Operand-memory reads for a load |
|---|---|---|
| Immediate | Operand = k, encoded in the instruction | 0 |
| Register | Operand = R[R] | 0 |
| Direct / absolute | EA = A; operand = M[A] | 1 |
| Register indirect | EA = R[R]; operand = M[EA] | 1 |
| Memory indirect | EA = M[A]; operand = M[EA] | 2 |
| Base plus displacement | EA = R[R] + d; operand = M[EA] | 1 |
Mode names and notation differ between ISAs. Here “memory indirect” specifically means one pointer read followed by one operand read. Additional levels of indirection would require their own definition. Calculating EA does not, by itself, load M[EA]. A store writes a source value to its computed EA rather than reading the destination as a load would.
4. Worked example: one state, several modes
Take R[R1]=500, M[500]=900, M[508]=21 and M[900]=37. Each row below starts from this same state.
- Immediate 500 gives operand 500, with zero operand-memory reads.
- Register R1 also gives 500, but the source is the register, not the instruction constant.
- Direct address 500 gives EA=500 and operand 900.
- Register indirect through R1 also gives EA=500 and operand 900.
- Memory indirect through address 500 gives EA=M[500]=900, then operand M[900]=37.
- Base R1 with displacement 8 gives EA=500+8=508 and operand 21.
Equal results in two rows do not make the addressing modes identical. Change the register or memory state and the results can differ.
5. Worked example: trace a load, add and store
At PC=100, execute LOAD R2, 8(R1), defined as R[R2] ← M[R[R1]+8]. With the state above, EA=508 and R[R2]=21; sequential PC becomes 104. Next, ADDI R2, 3 means R[R2] ← R[R2]+3, so R[R2]=24 and PC becomes 108. Finally, STORE R2, 12(R1) writes M[512]=24 and PC becomes 112.
The sequence makes one logical data-memory read and one data-memory write. Its three instruction fetches are additional memory references if a question asks for all references. The add reads and writes registers but makes no data-memory access. The store does not also read M[512] in this simplified semantic count.
6. Worked example: array scaling and a backward branch
An array of four-byte elements starts at byte address 800. Element a[5], using zero-based indexing, starts at 800+5×4=820. The index counts elements; the address displacement counts bytes. If an addressing rule already multiplies by a scale, do not multiply twice.
For a four-byte branch at address 200, define the target as the next sequential PC plus a signed byte displacement. With displacement −12, the target is (200+4)−12=192. If the question instead specified a displacement in four-byte instructions, −12 would mean −48 bytes. Never import an unstated convention from another ISA.
Key points and common mistakes
- Write EA first, then fetch M[EA] only if the operand is in memory.
- Distinguish direct memory, register indirect and memory indirect.
- State whether a count includes instruction fetch, data reads and data writes.
- Declare byte versus word addressing, operand size, instruction length and branch-PC convention.
- A conceptual execution step is not automatically a clock cycle.
- A load copies data into a register; a store copies a value to memory. Neither operation changes the base register here.
Original practice: six single-correct MCQs
These are original questions, not previous-year questions. Choose exactly one option.
I01. M[120]=44. What operands result from immediate constant 120 and direct address 120, respectively?
A. 44, 120 B. 120, 44 C. 120, 120 D. 44, 44
Answer: B
A: This reverses a literal constant and the contents of a memory location.
B: Immediate gives the encoded constant 120; direct addressing reads M[120]=44.
C: The direct operand is the stored word, not its address.
D: Immediate mode does not read M[120]; its value remains 120.
I02. In one-level memory-indirect addressing, the address field is 180, M[180]=400 and M[400]=9. What are the effective address and operand?
A. 180, 400 B. 9, 400 C. 400, 9 D. 180, 9
Answer: C
A: That is direct addressing through 180, not the specified indirection.
B: The pointer value 400 is the address; 9 is its contents, not the reverse.
C: First EA=M[180]=400; then operand=M[400]=9.
D: The final operand is 9, but its effective address is 400, not the original field 180.
I03. R[R3]=300 and M[288]=17. A load uses base R3 with signed byte displacement −12. Which EA/operand pair is correct?
A. 288, 17 B. 312, 17 C. 300, 288 D. 17, 288
Answer: A
A: EA=300+(−12)=288; reading that address obtains 17.
B: Adding the magnitude instead of the signed displacement gives 312 incorrectly.
C: The displacement changes the address; 288 is an address, not the given operand.
D: This exchanges the computed address and its contents.
I04. A four-byte branch starts at byte address 1000. Its target is the next sequential PC plus a signed byte displacement of −20. What is the target?
A. 980 B. 1024 C. 924 D. 984
Answer: D
A: This subtracts 20 from the current instruction address rather than the specified next PC.
B: The displacement is negative, so it must be subtracted from 1004.
C: This scales −20 by four even though it is already measured in bytes.
D: Next PC=1000+4=1004; target=1004−20=984.
I05. A load obtains a pointer from M[A], then reads the operand from the address held in that pointer. Excluding instruction fetches, caches and translation, how many logical data-memory reads are required?
A. 0 B. 2 C. 1 D. 3
Answer: B
A: Both the pointer and operand are in memory, so zero reads cannot obtain them.
B: One read obtains the pointer and a second obtains the operand.
C: One read obtains only the pointer, not the final operand.
D: The instruction fetch is excluded; no third data-memory read was specified.
I06. An array begins at byte address 600 and contains four-byte elements. What is the start address of element a[7] under zero-based indexing?
A. 607 B. 632 C. 628 D. 624
Answer: C
A: Seven is an element index; it must be multiplied by four bytes per element.
B: This uses eight element lengths even though index 7 is seven positions after index 0.
C: Address=600+7×4=628.
D: This uses index 6 instead of 7.
Sources and scope
This is an introductory Computer Organization lesson, not full-topic or full-syllabus completion. The official syllabus establishes alignment; technical references check the underlying definitions. Teaching models, worked examples and practice are original. Verified 14 October 2026.
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