Latches flip-flops and synchronous timing
A circuit that remembers
A combinational output is determined by the current inputs after settling. A sequential circuit also depends on stored state. The same present input can therefore produce different outputs after different histories. A storage element is not made predictable by simply drawing a feedback wire: its stable states, control signals and timing rules must be defined.
Prerequisites: NOR/NAND gates and Boolean equations. Goals: interpret SR and D storage contracts, distinguish a transparent latch from an edge-triggered flip-flop, trace sampled data, and check simple setup/hold inequalities. We assume ideal Boolean states outside transitions and explicitly stated timing parameters. Metastability, asynchronous design and clock-domain crossing need more detailed treatment than a truth table.
Active-high SR latch
A cross-coupled NOR SR latch has active-high set S and reset R. With S=1,R=0 it sets Q=1; S=0,R=1 resets Q=0; S=R=0 retains its previous stable Q. Let Q_next mean the settled state after the specified controls, not necessarily a clocked state.
| S | R | Q_next | Meaning |
|---|---|---|---|
| 0 | 0 | Q | Hold previous state |
| 0 | 1 | 0 | Reset |
| 1 | 0 | 1 | Set |
| 1 | 1 | Not a valid storage command | Forbidden condition |
For the NOR implementation, S=R=1 drives both cross-coupled outputs to 0, so they are no longer complements. If both controls are then released together, the resulting state is not guaranteed by the Boolean model. Do not label that condition “toggle” or assign a predictable next state. The latch may also start in an unspecified state; a reset operation establishes a known starting value.
An active-low NAND SR latch uses controls S_bar,R_bar instead. Its hold input is 11, set is 01 and reset is 10; 00 is forbidden. A bar in a signal's name means the control is active low, not a separate instruction to negate the truth-table row again. Always identify the implementation before using an SR table.
Worked example 1: a NOR latch starts at Q=0. Commands (S,R)=(1,0),(0,0),(0,1),(0,0) give Q=1,1,0,0. A hold command preserves the latest state, not the reset value forever.
D latch and transparency
An active-high D latch has data D and enable E. While E=1 it is transparent: after propagation delay Q follows changes in D. When E becomes 0 it retains the last valid value, provided the closing-edge timing requirements were met. In a Boolean model its relation is Q_next=ED+E′Q.
Conceptually deriving S=ED and R=ED′ prevents the ideal Boolean SR inputs from both being 1. This relation explains the functional contract; it is not an assurance that an arbitrary real gate implementation has no timing hazards. Real components must satisfy their specified timing requirements.
Worked example 2: initially Q=0,E=0. Changing D from 0 to 1 does not change Q. Raise E to 1 and hold D=1 long enough: Q becomes 1. While E stays 1, changing D to 0 makes Q become 0 after delay. Lower E with D stable at 0; later D=1 with E=0 leaves Q=0. A latch does not wait only for the rising edge of E while transparent.
Edge-triggered D flip-flop
A positive-edge-triggered D flip-flop samples D at each rising clock edge, subject to setup and hold. Its output changes to the sampled value after clock-to-Q delay and otherwise retains that value. During the remainder of the high clock level it is not transparent. Opposite-polarity latch stages can implement edge-triggered behavior, but the active edge depends on how those stages are connected.
Worked example 3: Q starts at 0. The valid D values at three rising edges are 1,0,1. After the corresponding clock-to-Q delays, Q is 1,0,1. A D pulse entirely between the first and second edges, absent at both sampling windows, is not captured. This is why a sampled waveform must identify edge times, not merely the order in which D changes.
Reset is a separate contract. A synchronous reset takes effect at the active clock edge. An asynchronous reset can assert its effect without waiting for that edge. Reset polarity and priority over data/enable must be stated. Asynchronous reset release has its own timing requirements; it is not permission to ignore all timing.
Setup hold and clock-to-Q
Setup time t_setup requires D to be stable before the capturing edge; hold time t_hold requires continued stability afterward. Clock-to-Q maximum delay t_CQ,max bounds when the new Q is guaranteed valid. A minimum delay t_CQ,min bounds how soon Q may start changing. They answer different questions; maximum delay cannot be substituted for minimum delay in a hold check.
A setup/hold violation does not imply a guaranteed wrong 0 or 1. It removes the timing guarantee and may cause metastability or capture of an unintended value. Slowing the clock may help a setup-limited path, but generally does not repair an overly short same-edge hold path.
Worked register-to-register timing
Assume positive-edge registers share an ideal clock, zero skew/jitter, and one-cycle data paths. For every launching-register to capturing-register path:
T ≥ t_CQ,max + t_logic,max + t_setup.
t_CQ,min + t_logic,min ≥ t_hold.
The first allows launched data to settle before the next edge. The second prevents newly launched data from disturbing the old value too soon after the current edge. Use the maximum of setup path requirements, but check the minimum-delay requirement for every relevant path.
Worked example 4: t_CQ,max=1 ns, t_logic,max=6 ns and t_setup=1 ns require T≥8 ns, so the model's maximum frequency is 1/(8 ns)=125 MHz. If t_CQ,min=0.2 ns, t_logic,min=0.3 ns and t_hold=0.7 ns, the hold arrival is 0.5 ns, short by 0.2 ns. A longer period alone does not change that sum. A repair must change the appropriate minimum-delay or clock relationship while preserving other constraints; this introductory example assumes zero skew throughout.
Key checks
Write the initial state, active controls, reset convention and observation time. For latches, trace the entire transparent interval. For flip-flops, sample only specified edges and use pre-edge inputs. Do not call every feedback circuit a safe memory, swap NAND/NOR SR tables, treat a forbidden input as a don't-care output to rely on, or infer physical timing from an ideal truth table.
Original practice
These six single-correct MCQs are original learning questions, not previous-year questions. Choose exactly one option.
C01. A NOR active-high SR latch has Q=1. What does S=R=0 do?
A. Resets Q to 0 B. Holds Q at 1 C. Toggles Q to 0 D. Forces both outputs to 0
Answer: B
A is incorrect: reset requires R=1,S=0.
B is correct: the 00 command holds the previous stable state.
C is incorrect: hold is not toggle.
D is incorrect: both outputs become 0 under the forbidden NOR command 11, not 00.
C02. Which is the forbidden simultaneous input for an active-low NAND SR latch?
A. S_bar=1,R_bar=1 B. S_bar=0,R_bar=1 C. S_bar=1,R_bar=0 D. S_bar=0,R_bar=0
Answer: D
A is incorrect: 11 is the hold command.
B is incorrect: 01 is set.
C is incorrect: 10 is reset.
D is correct: both active-low controls are asserted, giving the forbidden condition.
C03. While an active-high D latch remains enabled, D changes from 0 to 1 and stays stable. What happens to Q after propagation delay?
A. It remains 0 until the next rising enable edge. B. It follows D to 1. C. It necessarily toggles twice. D. Its value must be unknown.
Answer: B
A is incorrect: an enabled latch is transparent, not edge-triggered.
B is correct: during E=1, Q follows the stable data after delay.
C is incorrect: no toggle behavior was specified.
D is incorrect: valid stable inputs under the stated contract determine Q.
C04. A positive-edge D flip-flop starts at Q=0. Valid D values at two rising edges are 1 then 0. What are Q values after the respective clock-to-Q delays?
A. 0,1 B. 1,1 C. 1,0 D. 0,0
Answer: C
A is incorrect: this reverses the sampled values.
B is incorrect: the second edge samples 0.
C is correct: each edge captures its stated D value.
D is incorrect: the first edge captures 1, replacing the initial state.
C05. With zero skew, t_CQ,max=2 ns, logic maximum delay=5 ns and setup=1 ns, what is the minimum setup-safe period?
A. 8 ns B. 5 ns C. 6 ns D. 125 ns
Answer: A
A is correct: 2+5+1=8 ns.
B is incorrect: it omits clock-to-Q and setup.
C is incorrect: it omits clock-to-Q.
D is incorrect: 125 is the corresponding MHz frequency, not the period in ns.
C06. With zero skew, minimum clock-to-Q is 0.2 ns, minimum logic delay is 0.1 ns and hold time is 0.5 ns. Which statement is correct?
A. Hold passes because all delays are positive. B. Doubling the clock period necessarily fixes hold. C. Hold is violated by 0.2 ns in this model. D. Maximum logic delay must replace minimum logic delay in this check.
Answer: C
A is incorrect: 0.2+0.1=0.3 ns is below 0.5 ns.
B is incorrect: the same-edge earliest arrival is unchanged by period alone.
C is correct: 0.5−0.3=0.2 ns of required hold stability is missing.
D is incorrect: hold is an earliest-arrival check using minimum delays.
Scope and sources
This is one bounded Digital Logic lesson, not complete GATE CS coverage. The official syllabus establishes relevance only; the derivations, examples and practice are original. Technical references were used to check representation and circuit conventions, not to reproduce their exercises.
Sources checked 14 October 2026.
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