Ripple ring and Johnson counters

A counter is a specified state sequence

A counter's modulus is the number of states in its intended repeating cycle, not automatically 2^n just because it contains n flip-flops. Specify the clock edges, feedback equations, bit order, initial state and observation time before tracing it.

Prerequisites: flip-flops, shift registers, synchronous counters, finite-state machines and timing. These are selected sequential implementations within the broad syllabus clause, not separately enumerated official requirements. We compare an explicitly connected ripple binary counter with two shared-clock shift-register counters. Physical reset release, metastability and clock-domain synchronization are not solved by these ideal traces.

A falling-edge ripple binary counter

Use three T flip-flops with T=1, written Q_2Q_1Q_0. FF0 toggles on each falling edge of the external clock. FF1 toggles on each falling edge of Q_0; FF2 toggles on each falling edge of Q_1. All begin at 000, and each stage's output is observed after it settles. Q outputs, not complemented outputs, clock the next stage.

Each stage divides the frequency of its clock by two. With adequate settling and the stated connection, the stable sequence after successive external falling edges is 001,010,011,100,101,110,111,000. Q_0 has frequency f/2,Q_1 f/4,Q_2 f/8. Replacing a falling-edge trigger with a rising-edge trigger, or connecting Q′ instead of Q, can change the count direction; “ripple counter” alone does not determine its sequence.

The reason a higher bit toggles is the lower bit's 1→0 transition, representing binary carry. If Q_0 rises from zero to one, it does not clock FF1 in this design. Unlike a synchronous counter, these bits are not all triggered by one common clock edge. The final binary sequence can be correct even though intermediate output vectors are not the next stable count.

Trace the transient, not only the final count

Worked example 1: start at stable 011 and apply an external falling edge at t=0. Let every stage have exactly 4 ns clock-to-Q delay, with zero wire delay and no other edge during the trace.

Time interval	Visible Q_2Q_1Q_0	Cause
0≤t<4 ns	011	FF0 has not changed yet
4≤t<8 ns	010	Q_0 fell, triggering FF1
8≤t<12 ns	000	Q_1 fell, triggering FF2
t≥12 ns	100	Q_2 rose; final count is 4

A zero detector Q_2′Q_1′Q_0′ can therefore assert temporarily even though the initial count is 3 and final count is 4. Its actual pulse is additionally affected by decoder gate delays. The stable-state truth table does not remove this transient. Do not use an unqualified decoded output as a clean clock or asynchronous reset.

The longest all-stage ripple in this ideal three-stage model settles after 12 ns. A system that requires every count settled before the next external edge must budget at least that path delay, plus any decoder and sampling margins. This is not a complete maximum-clock-frequency specification for a physical chip; pulse widths, recovery/removal and loading also matter. A synchronous binary counter instead samples one shared edge but still needs its own next-state and register timing checks.

A straight ring counter

Now use three rising-edge D flip-flops on one common clock. Define a right-rotation explicitly:

D_2=Q_0, D_1=Q_2, D_0=Q_1.

All right-hand values are old state. With one-hot initialization 100, the sequence is 100→010→001→100. Exactly one bit is high in the intended cycle, so a state can be indicated directly by that bit. For n≥2 stages initialized with exactly one one, the ring has n states and each individual output pulse repeats every n clock periods. Ideally it is high for one period and low for n−1, giving duty cycle 1/n and frequency f/n.

Worked example 2: a five-stage one-hot ring clocked at 20 MHz produces each state-indicator pulse at 4 MHz with ideal 20% duty cycle. The register stores five bits but the intended sequence has five states, not 32. The remaining 2^n−n patterns are outside that intended one-hot cycle.

Plain rotation preserves the number of ones. Initializing our three-bit ring to 000 locks it at zero; 111 locks it at all ones. A two-one pattern circulates in a different cycle. Thus clearing all flip-flops is not sufficient to start a one-hot ring, and the plain feedback is not self-correcting. A separate valid-state detector and load path can recover to 100, but that is additional logic, not a property of rotation itself.

A Johnson counter uses complemented feedback

Keep the common rising clock and right shift, but complement the recirculated bit:

D_2=Q_0′, D_1=Q_2, D_0=Q_1.

Starting at 000 gives 000→100→110→111→011→001→000, six states. Ones fill the register for three edges and zeros then fill it for three more. In general, an n-stage Johnson counter initialized to all zeros has a 2n-state intended cycle. Each output is high for n periods and low for n periods, so ideal output frequency is f/(2n) and duty cycle 1/2. This is not an ordinary binary numerical count sequence.

Worked example 3: a four-stage Johnson counter at 24 MHz has eight intended states and each flip-flop output repeats at 3 MHz, with ideal 50% duty cycle. Eight states do not mean it stores only three flip-flops; its chosen implementation uses four.

Adjacent states in the intended Johnson cycle differ in one bit, including the wrap. This simplifies state decoding, but does not by itself certify arbitrary asynchronous use or faulty states. In our three-bit normal cycle, Q_2′Q_0′ identifies 000 among the six valid states. However, it also asserts for invalid state 010. A reduced decoder valid only on the normal cycle is not a unique detector over all eight possible patterns.

Unused states and explicit recovery

For the three-bit Johnson machine, the two states outside the normal cycle are 010 and 101. Under the plain equations they form their own cycle: 010→101→010. Thus a reset to 000 starts correct operation, but a later upset into either unused state does not automatically recover.

A fully specified synchronous recovery design can use bad=Q_2′Q_1Q_0′+Q_2Q_1′Q_0. At every edge, if bad=1 load 000; otherwise use the normal Johnson equations. Its D inputs are D_2=bad′Q_0′,D_1=bad′Q_2,D_0=bad′Q_1. All six intended transitions are unchanged and both invalid patterns reach 000 in one edge. Check all eight rows instead of declaring invalid states don't-cares and hoping the simplified result recovers.

Reset, if present, must have a specified priority over this choice. The proof is about sampled Boolean state transitions with settled combinational logic; it does not guarantee correction of analog timing violations, persistent faults or arbitrary control glitches.

Key points and common mistakes

Binary ripple, one-hot ring and Johnson counters use storage differently. For the stated normal cycles their state counts are 2^n,n and 2n, respectively. A ring needs one-hot initialization; an ordinary Johnson counter can start at all zeros. Neither plain feedback is guaranteed to recover from every invalid state. Trace actual edge polarities for ripple, use old-state simultaneous assignments for shared-clock registers, and separate settled count from intermediate waveform. Frequency and duty-cycle claims refer to the stated periodic normal operation, not reset transients.

Original practice

These six single-correct MCQs are original learning questions, not previous-year questions. Choose exactly one option.

C01. In the stated three-stage falling-edge ripple counter, stable 011 receives one external falling edge. What is the final settled count?

A. 010 B. 000 C. 100 D. 111

Answer: C

A is incorrect: 010 is only the first intermediate vector in the stated delay trace.

B is incorrect: 000 is an intermediate vector, not the final count.

C is correct: the specified falling-Q cascade increments binary 3 to 4.

D is incorrect: no rule toggles all stages merely because they exist.

C02. With exact 4 ns delay per stage, in the worked 011→100 ripple transition, when is the visible vector 000?

A. 8≤t<12 ns B. 0≤t<4 ns C. 4≤t<8 ns D. For all t≥12 ns

Answer: A

A is correct: Q_1 falls at 8 ns and Q_2 rises at 12 ns.

B is incorrect: the old vector 011 remains during the first interval.

C is incorrect: only Q_0 has fallen then, giving 010.

D is incorrect: after 12 ns the settled vector is 100.

C03. A plain three-bit ring uses D_2=Q_0,D_1=Q_2,D_0=Q_1. Starting from 000, what happens?

A. It automatically enters 100 after one edge. B. It counts all eight binary states. C. It enters the six-state Johnson cycle. D. It remains at 000.

Answer: D

A is incorrect: rotation does not create a one from all zeros.

B is incorrect: the equations rotate bits, not increment a binary integer.

C is incorrect: Johnson feedback complements a bit; this feedback does not.

D is correct: every D input is zero whenever every old Q is zero.

C04. For the stated three-bit Johnson equations, what is the next state after 110?

A. 011 B. 111 C. 100 D. 000

Answer: B

A is incorrect: that follows 111 in the normal cycle, not 110.

B is correct: D_2=NOT0=1,D_1=1,D_0=1.

C is incorrect: it discards the old Q_1 contribution to D_0.

D is incorrect: no reset or bad-state override applies to valid 110.

C05. A four-stage Johnson counter follows its all-zero-initialized normal cycle at 24 MHz. What are intended state count and each output frequency?

A. 16 and 1.5 MHz B. 4 and 6 MHz C. 8 and 3 MHz D. 8 and 6 MHz

Answer: C

A is incorrect: this uses all possible encodings, not the 2n-state Johnson cycle.

B is incorrect: this is the state count of a four-stage one-hot ring.

C is correct: 2n=8 and f/(2n)=24/8=3 MHz.

D is incorrect: an output period spans eight clock periods, not four.

C06. The three-bit Johnson recovery circuit loads 000 when bad=Q_2′Q_1Q_0′+Q_2Q_1′Q_0. What happens from 010?

A. It follows the ordinary transition to 101. B. It must remain 010 forever. C. It becomes 111 because bad means all ones. D. It reaches 000 at the next valid edge.

Answer: D

A is incorrect: the recovery override replaces the ordinary transition when bad=1.

B is incorrect: the explicit load defines a recovery edge.

C is incorrect: bad is a control predicate, not a data word to copy.

D is correct: the first product in bad is one for 010, so the defined load wins.

Scope and sources

This is one bounded Digital Logic lesson, not complete GATE CS coverage. The official syllabus establishes relevance only; the derivations, examples and practice are original. Technical references were used to check representation and circuit conventions, not to reproduce their exercises.

• Official GATE 2027 CS syllabus Section 2
• Purdue sequential counter feedback and recovery conventions
• Toshiba counter timing and ripple behavior

Sources checked 14 October 2026.