I/O interfaces interrupts and DMA
Learning objectives and scope
Separate device addressing, readiness notification and data movement; compare polling, interrupts and DMA; calculate CPU overhead and shared-bus occupancy. Prerequisites: datapath, memory addressing and CPU-time units. This is the I/O-interface slice of GATE 2026 COA, not a full OS driver, interrupt-controller or device-protocol treatment.
A device controller exposes data, status and control registers. A status bit may report ready/busy or completion; a control register may start an operation; a data register carries payload. Register meanings are device-specific. Reading or writing a device register can have side effects, so it is not always safe to treat it like ordinary RAM.
1. Three questions, three independent axes
Addressing: memory-mapped I/O assigns device registers addresses in the CPU's memory address space and uses appropriate load/store operations. Isolated/port-mapped I/O uses a separate I/O address space and special I/O instructions. Mapping a device register does not mean the device's entire storage is ordinary RAM.
Notification: polling repeatedly checks status in software; interrupts notify the CPU of an event so it can run an interrupt service routine (ISR). Data movement: programmed I/O uses CPU instructions to move each data item; DMA uses a controller/engine to transfer a configured block between device and memory. Interrupt-driven programmed I/O is possible, and DMA completion can be detected by polling or an interrupt. These choices are not mutually exclusive labels on one list. Memory-mapped I/O does not require DMA.
2. Polling trades CPU work for explicit checks
A busy-wait polling loop occupies CPU time while checking readiness. Polling at intervals reduces checking work but may delay discovery of completion. With a fixed period Δ and completion uniformly distributed between checks, detection delay averages Δ/2 and is less than or equal to Δ under the stated interval convention. Add actual check/handling time separately if it matters.
Worked overhead: 10000 polls/s, each costing 200 CPU cycles, on a 1 GHz CPU use 2 million cycles/s, or 0.2% of CPU capacity. This counts only the polls, not data-copy work or other instructions. A low percentage here does not establish low end-to-end device latency.
3. Interrupt handling costs something
An interrupt causes a transfer of control at an architecture-defined point. Hardware and software preserve the state required to resume, identify/service the event, acknowledge it as the device requires, and return. A priority mechanism selects among competing requests. Disabling a maskable interrupt can postpone handling; it does not necessarily stop the device or erase a pending event.
An interrupt is not automatically a process context switch. The handler might return to the same interrupted task; an OS may choose to schedule another task afterward. Likewise, one interrupt need not equal one byte: devices can batch events.
Worked overhead: 20000 interrupts/s costing 3000 cycles each consume 60 million cycles/s. On a 2 GHz CPU, that is 3% CPU capacity. If the same data can be batched into one interrupt for every ten prior events, fixed per-interrupt overhead becomes 0.3%, assuming the 3000-cycle fixed cost is unchanged. Per-byte work may remain, and batching can add latency.
4. DMA removes per-word CPU copying, not all CPU involvement
The CPU configures source/destination or direction, memory address, transfer count and required control state. The DMA engine arbitrates for the interconnect and moves data; completion is reported. CPU setup, synchronization and completion handling remain. DMA also consumes memory/interconnect bandwidth and can interfere with CPU accesses.
In a simple shared-bus model, burst DMA holds the bus for several transfers; cycle stealing grants individual transfer slots and lets CPU activity use other slots. The CPU need not stop all computation: register/cache work may continue when it does not require the occupied resource. Exact contention depends on the machine.
Worked transfer: 8 KiB=8192 bytes, bus width 4 bytes and one DMA word every 20 ns with no setup gaps. There are 2048 transfers and 40960 ns=40.96 µs of bus occupation. If DMA setup costs 500 cycles and completion 300 cycles on a 1 GHz CPU, CPU control overhead is 800 ns=0.8 µs. Bus time is not CPU instruction time. End-to-end completion depends on whether phases overlap; if setup, transfer and completion are strictly serial here, total is 41.76 µs.
5. Coherence and safe reasoning boundaries
A noncoherent DMA engine may read old memory while newer CPU data remains dirty in cache, or write memory while the CPU holds an old cached copy. A system needs suitable hardware coherence or software synchronization/cache maintenance. Details depend on the architecture; simply choosing DMA does not guarantee coherent results. This conceptual warning is not a prescription to flush every cache or use an arbitrary device barrier.
Worked comparison: CPU-copy programmed I/O costs 8 cycles/word for 2048 words, or 16384 CPU cycles. DMA control overhead of 800 cycles saves 15584 cycles of CPU involvement, under the stated costs. It does not prove the transfer finishes 20.48 times sooner; device/bus speed can dominate elapsed time in both methods.
Common mistakes
Do not confuse where registers are addressed with how payload moves. Interrupts save polling but create handling overhead. DMA is not zero CPU work and not zero bus use. Count words after converting bytes and width. Compare CPU utilization and elapsed latency separately, and state overlap assumptions before adding times.
Original practice: six single-correct MCQs
These original teaching questions are not previous-year questions. Choose exactly one answer.
P01. Which combination is possible?
A. Memory-mapped I/O with polling B. DMA only if no interrupts exist C. Interrupts only with DMA D. Memory-mapped I/O only with DMA
Answer: A
A: Address mapping and notification are independent choices.
B: DMA completion can use an interrupt.
C: An ISR can perform programmed I/O copying.
D: CPU loads/stores can access mapped device registers without DMA.
P02. 5000 polls/s cost 400 cycles each on a 1 GHz CPU. Polling-only CPU fraction?
A. 0.02% B. 0.2% C. 2% D. 20%
Answer: B
A: This loses a factor of ten.
B: 5000×400/10^9=0.002=0.2%.
C: The consumed cycles are 2 million, not 20 million.
D: This is one hundred times the correct fraction.
P03. Fixed checks every 100 µs, negligible check cost, completion uniformly between checks. Average detection delay?
A. 0 µs B. 25 µs C. 50 µs D. 100 µs
Answer: C
A: Some completions occur just after a check and must wait.
B: The uniform mean over 0 to 100 is 50, not 25.
C: Expected wait is half the polling interval: 50 µs.
D: 100 µs is the upper bound, not the mean.
P04. A 4 KiB DMA transfer uses four-byte words, one per 10 ns, without gaps. Bus occupation time?
A. 40.96 µs B. 10.24 µs C. 1.024 µs D. 4 µs
Answer: B
A: This treats every byte as a full-word transfer.
B: 4096/4=1024 transfers; 1024×10 ns=10.24 µs.
C: There is a factor-of-ten time error.
D: The binary byte count and given word period must both be used.
P05. Which statement about an interrupt is correct?
A. It must switch to a different process B. It has zero handling cost C. Its handler may return to the interrupted task D. It always transfers exactly one byte
Answer: C
A: An interrupt handler can resume the same task.
B: Saving state and servicing an event consume work.
C: A process context switch is not required for every interrupt.
D: Devices can batch data or signal non-data events.
P06. CPU copy costs 6 cycles/word for 1000 words. DMA setup plus completion costs 500 cycles. CPU cycles saved?
A. 500 B. 5500 C. 6000 D. 6500
Answer: B
A: 500 is the remaining DMA CPU cost, not the saving.
B: CPU copy=6000; saving=6000−500=5500 cycles.
C: DMA still needs 500 cycles of CPU control work.
D: This adds costs instead of subtracting.
Sources and scope
Aligned to the 2026 course. This lesson covers the stated slice, not the entire COA syllabus. All numerical examples and questions are original. No claim of 2027 completeness.
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