Datapath register transfers and control
Learning goals and machine contract
Trace a register, load and store instruction through a datapath; derive control signals from intended state changes; compare single-cycle and multicycle control. Prerequisites: the existing instruction/addressing lesson and basic multiplexers/registers. Gate construction and arithmetic algorithms belong to the existing Digital Logic lessons and are not repeated here.
Our teaching ISA has 32-bit registers, byte-addressed memory, fixed four-byte instructions, aligned valid accesses and no exceptions or overflow. ADD Rd,Rs,Rt means R[Rd]←R[Rs]+R[Rt]; LD Rd,d(Rs) loads a word at R[Rs]+d; ST Rt,d(Rs) stores R[Rt] there. The signed displacement d is already decoded. This is a specified educational ISA, not a claim about a commercial ISA.
1. Separate values from decisions
A datapath contains storage, arithmetic/logic units, multiplexers and connections. Control tells it which operands to select and which state elements may change. A combinational ALU output alone does not change architectural state. The register or memory write enable must authorize the update at the relevant time.
For a simple single-cycle design, use a register file with two read ports and one write port; separate instruction and data memories; an ALU for register arithmetic or effective-address addition; and a dedicated PC+4 adder. A mux chooses register operand Rt or displacement d as the ALU's second input. A writeback mux chooses ALU result or memory data. These hardware choices are assumptions, not universal requirements.
2. Derive a control table instead of memorizing bits
Define RegWrite and MemWrite as active-high enables, MemRead as a data-memory read request, ALUSrc=0 for Rt and 1 for d, and MemToReg=0 for ALU output and 1 for memory output. For this subset ALU operation is ADD.
- ADD: RegWrite=1, MemRead=0, MemWrite=0, ALUSrc=0, MemToReg=0.
- LD: RegWrite=1, MemRead=1, MemWrite=0, ALUSrc=1, MemToReg=1.
- ST: RegWrite=0, MemRead=0, MemWrite=1, ALUSrc=1, MemToReg=X.
X means either selection gives the same architectural result because register writing is disabled. It does not mean an unknown value may be used by an enabled destination. For a store, Rt feeds the memory-data input even though the ALU chooses d for its second operand.
Worked trace: initially R1=100, R2=7, M[112]=25. LD R3,12(R1) computes 112, reads 25, and writes R3=25. ST R2,12(R1) also computes 112 but writes M[112]=7; it does not change R2 or R1. ADD R4,R1,R2 writes 107 into R4 and never writes data memory. Each non-branch advances PC by 4.
3. Clock timing follows the longest active path
In a single-cycle processor, all supported instructions complete in one clock period, so the clock must accommodate the slowest supported path, not the average path. Assume the load path has serial delays: instruction read 200 ps, register read 100 ps, ALU 150 ps, data read 250 ps, writeback mux/setup 50 ps. Decode and other selections fit within these listed stages; PC update is shorter. The required period is at least 750 ps. An ADD path of 500 ps still occupies this 750 ps cycle. Do not apply this sum to a design where stages operate in parallel or additional delays are unlisted.
4. Multicycle execution and control sequencing
A multicycle design splits an instruction into steps, retaining intermediate values in registers such as IR (instruction), A/B (operands), ALUOut and MDR (memory data). A possible load sequence is fetch; decode/read; address calculation; memory read; writeback. A store ends with memory write and needs no register-writeback step. A shared ALU may compute PC+4 in fetch and an address in a later cycle. Sharing hardware is safe when uses do not demand it simultaneously.
Worked timing: with a chosen 250 ps clock period that accommodates every step including all required register/clock overhead, a five-cycle load takes 1250 ps; a four-cycle store takes 1000 ps. Shorter cycles do not by themselves make every instruction faster than the 750 ps single-cycle design. Multicycle operation is not pipelining: without overlap, the next instruction waits.
Hardwired control uses logic and, for multicycle operation, a state machine to produce control signals. Microprogrammed control sequences control words held in a control store. A microinstruction controls implementation steps; it is not necessarily a programmer-visible instruction. Neither method changes the ISA semantics. Hardwired is not synonymous with single-cycle, and microprogrammed does not imply every ISA instruction has the same cycle count.
Checkpoints and common errors
- Track both the value and its destination; an effective address is not loaded data.
- A store writes memory, not its source register. Disable unintended writes explicitly.
- The load writeback mux must choose memory data, not the ALU-generated address.
- A mux setting can be irrelevant only when no enabled state change depends on it.
- Compare total execution time, not only cycle duration or cycle count.
Original practice: six single-correct MCQs
These original teaching questions are not previous-year questions. Choose exactly one answer.
P01. In the specified datapath, LD R5,8(R1) has R1=64 and M[72]=19. What is written into R5?
A. 8 B. 64 C. 72 D. 19
Answer: D
A: 8 is the displacement.
B: 64 is the base value.
C: 72 is the effective address, not loaded data.
D: Address=64+8=72; memory data at 72 is 19.
P02. Which control tuple (RegWrite, MemWrite, ALUSrc) implements ST in this model?
A. (1,0,1) B. (0,1,1) C. (0,1,0) D. (1,1,1)
Answer: B
A: This enables register write instead of memory write.
B: A store writes memory, disables register write and adds displacement.
C: ALUSrc=0 chooses Rt instead of displacement for the address.
D: RegWrite=1 permits an unintended register change.
P03. Why is MemToReg a don’t-care for ST here?
A. Memory is never accessed B. The ALU is unused C. Register writing is disabled D. All mux inputs are equal
Answer: C
A: ST accesses data memory to write.
B: The ALU calculates the effective address.
C: The writeback mux output cannot update a register when RegWrite=0.
D: The inputs need not be equal; the destination write is disabled.
P04. A single-cycle design has supported paths of 420, 600 and 780 ps, including all required overhead. Minimum safe clock period?
A. 420 ps B. 600 ps C. 780 ps D. 1800 ps
Answer: C
A: The shortest path cannot set the period.
B: This excludes the longest path.
C: The maximum supported path is 780 ps.
D: Their sum is not needed: different instruction paths do not execute serially in one instruction.
P05. A non-overlapped multicycle load takes five 200 ps cycles. Its latency is:
A. 200 ps B. 1000 ps C. 40 ps D. 800 ps
Answer: B
A: One cycle is only one step.
B: Five cycles ×200 ps=1000 ps.
C: Dividing cycle time by stage count is invalid.
D: Four cycles omit one of the five specified steps.
P06. Which statement about control is correct?
A. Hardwired control must be single-cycle B. A microinstruction is always an ISA instruction C. Microprogrammed control cannot implement loads D. Hardwired control can use a state machine
Answer: D
A: Hardwired control can sequence multiple cycles.
B: Microinstructions describe implementation-level control.
C: A microprogram can sequence a load’s operations.
D: A state machine can select control outputs and next states across cycles.
Sources and scope
Aligned to the 2026 course. This lesson covers the stated slice, not the entire COA syllabus. All numerical examples and questions are original. No claim of 2027 completeness.
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