Instruction encoding field budgets and branch ranges
Objectives and explicit contracts
Allocate bits to opcode/register/immediate fields, count unambiguous expanding opcodes, and decide whether a signed scaled branch target can be represented. Prerequisites: existing addressing lesson, binary integers and two's-complement range. This extends machine-instruction reasoning without reteaching number representation. Each example specifies its own educational encoding; do not import real MIPS/RISC-V bit layouts.
An ISA instruction has semantics; its encoding is a bit pattern the decoder interprets. An operand field naming a register contains a register number, not the register's data. Naming R registers requires ceil(log2 R) bits when all register names must fit. If R is not a power of two, some patterns can be unused or reserved. A maximum capacity of 2^b patterns does not imply every pattern is a valid implemented operation.
1. Account for every bit once
For a fixed W-bit format with opcode width o, r register fields each of width g, and no other fields, remaining immediate width is W−o−rg. If mode/function/reserved bits exist, subtract those too. Opcode bits and function bits can jointly identify an operation; do not assume the primary opcode alone names each operation in all ISAs.
Worked budget: a 24-bit teaching format supports 32 registers, two explicit register operands, a 6-bit opcode and no other fields. Each register field needs five bits, so immediate width=24−6−10=8 bits. Its unsigned range is 0..255 or signed two's-complement range −128..127 according to the instruction definition. There can be at most 64 distinct primary opcode patterns. If the machine increases its total register count from 32 to 64 while retaining two register fields and opcode width, each register field grows to six bits and the immediate shrinks to six bits. More register names compete for a fixed encoding budget.
Instruction width does not equal register width or address width. A 16-bit instruction can operate on 32-bit registers; a short displacement may combine with a full-width base register to address far more memory than its own range.
2. Expanding opcode fields without ambiguous decoding
Consider 16-bit instruction words divided into four 4-bit fields. A three-register instruction uses a 4-bit opcode plus three register names. Reserve 12 of the 16 first-field patterns for these instructions; the remaining four patterns are escapes for a two-register format. Under each escape, the next four bits extend the opcode, leaving two register fields. Thus there are 4×16=64 possible two-register operation codes, not 256: prefixes consumed by the three-register format are unavailable.
Now use 60 of those 64 extended operation codes for two-register instructions. Reserve the remaining four as escapes to a one-register format: the third 4-bit field extends the opcode further and the last field names the register. This gives 4×16=64 possible one-register operations. The count is operations, not complete machine-code words; each operation can have many operand combinations. The decoder reads the prefix to determine how the remaining fields are interpreted. A prefix cannot simultaneously identify an ordinary shorter opcode and an escape under this contract.
Independent count check: three-register encodings use 12×16^3=49152 words; two-register encodings use 60×16^2=15360; one-register encodings use 64×16=1024. Total=65536=2^16. No words overlap and all available bit patterns are allocated in this example.
3. Scaled signed branch fields
For this separate branch example only, instructions occupy four bytes and the branch at address P uses target=(P+4)+4d, where d is an 8-bit signed integer. The base is the next sequential PC; the scale is four bytes. The encoded integer range is −128..127, so byte displacement is −512..508 in multiples of four. Positive and negative limits are asymmetric.
Worked forward calculation: P=1000, encoded bits 11110101 represent −11. Target=1004+4(−11)=960. The encoding does not mean subtract eleven bytes; it means subtract eleven four-byte units.
Worked inverse calculation: for desired target T, compute d=(T−(P+4))/4. It must be an integer within −128..127. At P=1000, the representable targets range from 492 to 1512, in steps of four. Target 1516 is aligned but outside range (d=128). Target 1002 is numerically close but not representable because d=−0.5. Target 960 gives d=−11 and unsigned 8-bit encoding 256−11=245=0xF5. No address wraparound is allowed in these examples.
4. Distinguish reach, capacity and code size
The 8-bit branch field has 256 encodings and hence 256 possible target positions for a fixed P. It does not reach every byte in a 1024-byte contiguous interval. The smallest and largest reachable addresses differ by 1020 bytes. A word-scaled displacement is not a byte-address field, and an opcode count is not an instruction count in a program.
Common mistakes and checklist
List word width, every explicit/implicit field, register count and reserved prefixes. In branch questions, write base, signed width and scale before calculating. For inverse encoding check divisibility before range. Keep patterns, operations and operand combinations distinct. These formats teach 2026 machine-instruction depth; they are not a prediction of later syllabus or a real ISA specification.
Original practice: six single-correct MCQs
These original teaching questions are not previous-year questions. Choose exactly one answer.
P01. A 32-bit format has a 6-bit opcode, three register fields selecting among 32 registers, and only an immediate in the remaining bits. Immediate width?
A. 5 bits B. 11 bits C. 15 bits D. 26 bits
Answer: B
A: Each register field needs five bits, not the whole remaining immediate.
B: 32−6−3×5=11 bits.
C: 15 bits are consumed by all three register fields.
D: 26 ignores all register fields.
P02. How many bits are needed to encode 24 distinct register names?
A. 4 B. 5 C. 6 D. 24
Answer: B
A: Four bits name only sixteen registers.
B: ceil(log2 24)=5; some of 32 patterns remain unused.
C: Six works but is not the minimum.
D: A binary encoded index does not need one bit per register.
P03. A 16-bit word uses 4-bit fields. Fourteen primary opcodes use three register fields; the remaining two prefixes extend by four bits for two-register operations. Maximum two-register operations?
A. 16 B. 32 C. 224 D. 256
Answer: B
A: There are two escape prefixes, each with sixteen extensions.
B: (16−14)×16=32 distinct operation codes.
C: 224 counts occupied prefixes times sixteen, not available extensions.
D: All sixteen prefixes are not available.
P04. Branch at P=200 uses target=P+4+4d, with signed 6-bit d. Largest reachable target without wraparound?
A. 328 B. 332 C. 452 D. 235
Answer: A
A: Maximum d=31; target=204+124=328.
B: This incorrectly permits d=32.
C: This would use d=62, outside the signed six-bit range −32..31.
D: This adds 31 bytes and ignores scale four.
P05. At P=1000, target=P+4+4d with signed 8-bit d. Which target is not representable?
A. 492 B. 960 C. 1512 D. 1516
Answer: D
A: d=−128 is the valid minimum.
B: d=−11 is valid.
C: d=127 is the valid maximum.
D: d=(1516−1004)/4=128 exceeds the signed maximum.
P06. At P=1000, target=960 under target=P+4+4d. The 8-bit two’s-complement encoding of d is:
A. 0x0B B. 0xD4 C. 0xF5 D. 0xF6
Answer: C
A: 0x0B encodes +11, not −11.
B: 0xD4 encodes −44, the byte displacement before dividing by four.
C: d=(960−1004)/4=−11; 256−11=245=0xF5.
D: 0xF6 encodes −10, giving target 964.
Sources and scope
Aligned to the 2026 course. This lesson covers the stated slice, not the entire COA syllabus. All numerical examples and questions are original. No claim of 2027 completeness.
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