Main memory banks chips and secondary storage
Objectives and scope
Calculate memory capacity and chip organization, map word addresses to interleaved banks, distinguish latency from sustained bandwidth, and estimate magnetic-disk service time. This covers the main/secondary-memory slice of the GATE 2026 scope; it is not a complete storage-system course. Prerequisites: binary units and basic memory addressing. Cache address fields and OS page replacement are covered elsewhere.
Use 1 KiB=1024 bytes and 1 MiB=2^20 bytes. For chip labels, K means 2^10 addressable locations. A chip labelled 64K×8 stores 65536 locations of eight bits each, hence 64 KiB. State whether an address counts bytes or words before computing address bits or bank number.
1. SRAM and DRAM at the organization level
Conventional SRAM holds state in a powered bistable circuit and needs no periodic refresh; conventional DRAM stores charge and needs refresh to preserve data. Both are volatile: lack of DRAM-style refresh does not make SRAM retain data without power. SRAM is commonly used for caches, while denser DRAM is commonly used for main memory. These are technology tendencies, not a rule that every cache/main-memory device must use one technology.
DRAM organizes cells in rows and columns. Activating a row places its data in a row buffer; accesses to the open row differ from accesses needing a different row. Therefore a single quoted latency may hide row-hit, row-conflict and refresh effects. For arithmetic here, use the explicit fixed timing model; do not invent real-device timings.
2. Compose width and depth separately
To build N words of w bits using chips with n words of b bits, require w/b chips in parallel for word width and N/n groups for address depth, assuming exact divisibility. Total chips=(N/n)(w/b). Parallel chips share address signals but contribute different data bits; depth groups require selection.
Worked example: build 256K×32 using 64K×8 chips. Width expansion is 32/8=4 chips per group; depth expansion is 256K/64K=4 groups; total=16 chips. Capacity is 256K×4 bytes=1 MiB. There are 18 word-address bits: 16 select a location within each chip, 2 select a depth group. If the same memory is byte-addressable, 20 byte-address bits cover it; the lowest two identify byte position inside a 32-bit word. Word and byte address widths are not interchangeable. We exclude parity/ECC and control pins from the data-chip count.
3. Low-order bank interleaving
For B equal banks and word address a, low-order interleaving uses bank=a mod B and local word index=floor(a/B). With four banks, sequential word addresses 0,1,2,3,4 go to banks 0,1,2,3,0. For a=27, bank=3 and local index=6; reconstruction 6×4+3=27 checks the result. If an address is in bytes and each word is four bytes, first convert an aligned address to word number by dividing by four.
A stride of B words repeatedly selects one bank, limiting overlap. Banking primarily raises throughput when requests distribute across banks; it does not automatically divide a single request's latency by B.
Worked schedule: four independent banks each need 40 ns between request starts. The command/data path can sustain one request every 10 ns, and requests return after 40 ns with no further transfer cost. Sequential requests can start at 0,10,20,30,40 ns, rotating banks. After startup, bandwidth is one four-byte word/10 ns=400 MB/s in decimal units. A stride-four stream uses one bank and can start only every 40 ns: 100 MB/s. The first response latency remains 40 ns in either case. This simplified schedule is not a DDR timing specification.
4. Secondary storage and disk service time
Secondary storage retains data without power; HDDs and SSDs have different mechanisms. An HDD must position a head and wait for rotation. An SSD has no mechanical seek/rotation, but still has controller, flash and queueing costs. Never apply RPM formulas to an SSD.
For an isolated magnetic-disk read with no queue, no cache hit and no overlap, service time=seek+rotational wait+transfer+specified controller overhead. For uniformly random rotational arrival, expected rotational wait is half a revolution. At r RPM, one revolution=60/r seconds; average rotational wait=30/r seconds. This is an expectation, not a fixed cost for every request.
Worked example: at 6000 RPM, one revolution is 10 ms and average rotational wait is 5 ms. Mean seek is 4 ms, contiguous transfer is 200000 bytes at 100000000 bytes/s (=2 ms), controller overhead is 0.5 ms. Expected service time=4+5+2+0.5=11.5 ms. Queueing, a cache hit or a track crossing could change observed response time; they were explicitly excluded. Use decimal MB/s or binary MiB/s consistently rather than mixing them.
Common mistakes
Width expansion and depth expansion both count. Do not confuse addressable locations with bits. Convert byte addresses before word-bank calculations. Refresh and volatility are separate concepts. Banking changes available overlap, not an inherent per-request latency. Disk service time excludes queueing unless the problem includes it.
Original practice: six single-correct MCQs
These original teaching questions are not previous-year questions. Choose exactly one answer.
P01. How many 32K×8 chips build a 128K×32 memory, excluding ECC?
A. 4 B. 8 C. 16 D. 32
Answer: C
A: Four gives only the width or only the depth expansion.
B: Both independent factors are four, not four and two.
C: (128K/32K)×(32/8)=4×4=16.
D: This doubles the required capacity.
P02. A 64K×16 chip stores how many bytes?
A. 64 KiB B. 128 KiB C. 1 MiB D. 16 KiB
Answer: B
A: Each location is two bytes, not one.
B: 65536×16/8=131072 bytes=128 KiB.
C: It stores 1 Mibit, not 1 MiB.
D: Sixteen is bits/location, not KiB capacity.
P03. Eight banks use low-order interleaving of word addresses. Word address 45 maps to (bank, local index):
A. (5,5) B. (5,6) C. (6,5) D. (1,45)
Answer: A
A: 45=5×8+5, so remainder and quotient are both 5.
B: The quotient is floor(45/8)=5, not 6.
C: Bank is remainder 5, not rounded quotient 6.
D: The local index is not the unchanged global address.
P04. Which statement about conventional SRAM and DRAM is correct?
A. Both retain data without power B. SRAM needs DRAM-style periodic refresh C. DRAM needs refresh; both are volatile D. DRAM cannot be main memory
Answer: C
A: Both are volatile.
B: Powered SRAM does not require DRAM-style refresh.
C: DRAM refresh preserves charge while powered; neither inherently retains state without power.
D: DRAM is commonly used for main memory.
P05. For uniformly random rotational arrival at 7200 RPM, expected rotational latency is approximately:
A. 8.333 ms B. 4.167 ms C. 0.139 ms D. 7.2 ms
Answer: B
A: This is a full revolution, not its expected half.
B: 30/7200 seconds≈0.004167 seconds=4.167 ms.
C: RPM must be converted using 60 seconds/minute.
D: The numeric RPM value does not directly give milliseconds.
P06. Four-byte words start every 20 ns in a sustained interleaved stream. Decimal bandwidth?
A. 50 MB/s B. 200 MB/s C. 800 MB/s D. 20 MB/s
Answer: B
A: 50 million is words/s; each has four bytes.
B: 4/(20×10^−9)=200×10^6 bytes/s=200 MB/s.
C: This uses sixteen bytes per request instead of four.
D: Time interval and bandwidth cannot be equated numerically.
Sources and scope
Aligned to the 2026 course. This lesson covers the stated slice, not the entire COA syllabus. All numerical examples and questions are original. No claim of 2027 completeness.
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