Pipeline hazards forwarding stalls and flushes
Learning goals and precise pipeline contract
Identify structural, data and control hazards; schedule dependencies with and without forwarding; distinguish a stall from a flush; calculate a stated branch penalty. Prerequisites: pipeline timing and register-transfer lessons.
Use an in-order single-issue IF–ID–EX–MEM–WB pipeline. Each stage lasts one cycle. Register operands are read in ID; results write in WB. A WB write occurs early enough for ID to read that value in the same cycle. ALU results are ready at the end of EX; load data at the end of MEM. Forwarding, when enabled, supplies either ALU input at the beginning of EX from earlier pipeline registers; it cannot travel backward in time. Separate instruction/data memories avoid their structural conflict unless a question explicitly replaces them. No branch delay slots or out-of-order execution. These assumptions determine the numerical stall answers.
1. Dependence is a program relation; hazard depends on timing
If I1 writes R1 and later I2 reads R1 with no intervening write, I2 has a read-after-write (RAW) dependence on I1. A dependence does not always force a stall: sufficient separation or forwarding can deliver the correct value in time. Write-after-read (WAR) and write-after-write (WAW) are name-dependence categories; in this fixed-latency in-order pipeline, all reads occur in ID and writes in WB in order, so WAR/WAW do not cause execution hazards. That conclusion need not hold with out-of-order or variable-latency operations.
A structural hazard is competition for one insufficient hardware resource. A data hazard risks use of an unavailable correct operand. A control hazard arises because the next correct instruction address is unresolved. The same program can face different stalls on different implementations.
2. Adjacent ALU dependence
I1: ADD R1,R2,R3; I2: SUB R4,R1,R5. Without stalls, I1 has IF1 ID2 EX3 MEM4 WB5; I2 has IF2 ID3 EX4 MEM5 WB6. I1's ALU value exists after EX3, so forwarding can feed I2 at EX4 with zero stalls.
Without forwarding, I2 must stay in ID through cycle 5 to read R1 when I1 writes it. It enters EX6. Relative to intended EX4, two stall cycles were inserted. The early-write/late-read register convention is essential; a different convention could require another stall. A stall holds the waiting instruction and freezes upstream progress while older work continues; a bubble prevents the held instruction from executing prematurely.
3. Load-use dependence cannot be solved by that same bypass
I1: LD R1,0(R2); I2: ADD R3,R1,R4. I1's data is available only after MEM4. I2 would need it at the beginning of EX4, too early. With forwarding, insert one stall: I2 enters EX5 and consumes the MEM4 result. Without forwarding, it waits for WB5 and enters EX6, requiring two stalls in this model.
Scheduling can fill the gap with an independent useful instruction. Moving an ADD of unrelated registers between the load and consumer can remove the load-use bubble, provided it preserves all register/memory dependencies, control behavior and relevant exception semantics. Independence is a semantic condition, not simply different instruction names.
4. Forward the newest applicable value
I1: ADD R1,R2,R3; I2: ADD R1,R1,R4; I3: SUB R5,R1,R6. At I3's EX, both older pipeline registers may contain values associated with R1. I3 needs I2's newer value, not I1's stale one. The closer valid producer wins. Only a producer that actually writes the register and has the required data ready is eligible. Matching a destination number alone is insufficient; a load address in EX/MEM is not the loaded value.
5. Structural conflicts and branch flushes
With one single-ported shared instruction/data memory, a load's MEM request can conflict with another instruction's IF request. The implementation must arbitrate, stall or provide more bandwidth. Forwarding register values cannot resolve a memory-port conflict.
For a separate branch example, assume prediction is not-taken, branches resolve at the end of EX, and target fetch starts in the next cycle. When a taken branch is in EX, two younger fall-through instructions occupy ID and IF. They are wrong-path work and must be flushed before they make architectural changes. The penalty is two lost issue slots under these assumptions. An untaken branch correctly predicted this way incurs no such flush. A branch operand dependency could add other stalls; exclude those when computing this isolated penalty.
Worked long-stream example: branches are 20% of useful instructions; 30% of branches are mispredicted; each misprediction adds 2 cycles, and all other costs are absent. Extra CPI=0.20×0.30×2=0.12, so steady CPI=1.12. Do not use 30% as the fraction of all instructions. Finite-batch timing still adds the initial k−1 cycles, and overlapping penalties must not be counted twice.
Common traps
Forwarding cannot create a value before it exists. Stall counts require stage, availability and consumption times. A flush discards wrong-path instructions; a stall retains a correct instruction for later. Dependence and hazard are not synonyms. Branch penalty depends on resolution stage, prediction and fetch timing, not solely on pipeline depth.
Original practice: six single-correct MCQs
These original teaching questions are not previous-year questions. Choose exactly one answer.
P01. Under the stated full-forwarding model, adjacent ALU producer and ALU consumer need how many stalls?
A. 0 B. 1 C. 2 D. 3
Answer: A
A: EX result at end of cycle 3 can feed the next EX at start of cycle 4.
B: One stall is typical of the specified load-use case, not this ALU case.
C: Two stalls apply here when forwarding is absent.
D: No wait for a later register read is needed with this bypass.
P02. Under the stated forwarding model, an immediately dependent load-use pair needs how many stalls?
A. 0 B. 1 C. 2 D. 4
Answer: B
A: Load data is not ready at the consumer’s original EX start.
B: One bubble moves consumer EX from cycle 4 to cycle 5.
C: Two stalls are unnecessary with MEM-to-EX forwarding.
D: The consumer need not wait four extra cycles.
P03. With no forwarding and same-cycle WB-write/ID-read, adjacent ALU-dependent instructions need how many stalls?
A. 0 B. 1 C. 2 D. 3
Answer: C
A: ID3 would read the old value.
B: ID4 is still before WB5.
C: Consumer waits through ID5 and executes in EX6 instead of EX4: two stalls.
D: Three would ignore the permitted same-cycle WB/ID access.
P04. A load MEM access and an IF access compete for one single-ported memory. Which hazard is this?
A. RAW data B. Structural C. Control D. WAW
Answer: B
A: No register dependence is required for this conflict.
B: Both need the same insufficient hardware port.
C: The next-PC decision is not the cause.
D: There are not two ordered writes to the same register in this description.
P05. 25% of instructions are branches; 20% of branches are mispredicted. Each adds 3 cycles; no other penalties. Steady CPI?
A. 1.05 B. 1.15 C. 1.60 D. 1.75
Answer: B
A: 0.05 is mispredictions/instruction; each costs three cycles.
B: 1+0.25×0.20×3=1.15.
C: This applies 20% to all instructions instead of to branches.
D: This charges every branch the penalty.
P06. For ADD R1,R2,R3; ADD R1,R1,R4; SUB R5,R1,R6, which value of R1 must the SUB use?
A. Value before both ADDs B. First ADD result C. Second ADD result D. Either ADD result
Answer: C
A: Both earlier writes change the required program value.
B: The first result is superseded by the second write.
C: The latest preceding writer is the second ADD.
D: The results need not be equal; program order chooses the second.
Sources and scope
Aligned to the 2026 course. This lesson covers the stated slice, not the entire COA syllabus. All numerical examples and questions are original. No claim of 2027 completeness.
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