Micro-operation scheduling and control-store design
Learning objectives and model boundaries
Schedule register transfers on a resource-limited datapath, sequence a conditional microprogram, and calculate control-word/control-store size. Prerequisites: lesson 04 datapath and control plus basic binary field widths. This deepens the 2026 control-unit topic without repeating gate construction or instruction pipelining. It does not claim one universal control-word layout.
A micro-operation is an implementation-level action such as transferring a register or latching an ALU result. Several can occur in one clock only if resources, dependencies and timing allow them. All registers in our examples capture on the ending edge of a cycle; combinational inputs during that cycle use the old register outputs. A destination updated on an edge cannot retroactively supply its new value earlier in that same cycle.
1. A one-bus execution schedule
Specify one internal bus. At most one of R1,R2,R3,Z may drive it per cycle. Y can capture the bus; the ALU has input A=Y and input B=bus, and Z can capture the ALU result at the ending edge. R3 can capture the bus. There is no direct ALU-to-R3 path, no second bus, and no register bypass. All operations fit the stated clock period.
To implement R3←R1+R2:
- Cycle 1: R1 drives bus; Y captures R1.
- Cycle 2: R2 drives bus; ALU computes old Y+bus; Z captures R1+R2.
- Cycle 3: Z drives bus; R3 captures the result.
For R1=9 and R2=6, Y becomes 9, then Z becomes 15, then R3 becomes 15. R1/R2 remain unchanged. R1 and R2 cannot both drive the single bus in cycle 1. Combining cycle 1 and 2 is invalid because the ALU would see old Y, and the two source drives would conflict. Combining cycles 2 and 3 is invalid because Z's new result is not available until the ending edge and there is no bypass. Three cycles are therefore required under this contract; adding a second bus or direct path can change the answer.
2. Legal parallel transfers depend on wiring
Two destinations may capture one bus value simultaneously if each has an independent write enable and no other restriction. Thus R1→Y and R1→MAR can share a cycle in a datapath that provides both inputs and enables. They are a broadcast of one source, not two drivers. Conversely, R1→Y and R2→MAR require two distinct simultaneous source values, impossible on this one bus.
A control encoding can restrict parallelism even if wires would support it. If destination controls are placed in an encoded field allowing only one destination per cycle, the broadcast above is no longer expressible in one control word. Count legal actions before choosing an encoding.
3. Sequence control steps explicitly
A control address register (micro-PC) selects a word in the control store. That word selects datapath actions and how to select the next microaddress. This micro-PC is distinct from the architectural PC, which selects program instructions. Dispatch maps the decoded ISA instruction to its microprogram entry; it need not equal the instruction's opcode numerically.
Worked conditional sequence: at microaddress 10, latch Z←Y−bus and latch a Zero flag from that result; next address is 11. At 11, perform no datapath write and select next address 20 if the latched Zero=1, otherwise 30. At 20 choose an action for equal operands; at 30 choose the unequal path. If Y=7 and bus=7 in step 10, Zero becomes 1 at its ending edge and step 11 selects 20. This two-step sequence deliberately reads a latched flag. A design with same-cycle combinational condition routing could branch sooner, but that path is not assumed here. Do not silently use a newly computed flag before its defined availability.
4. Control-word width is a specified design calculation
Example encoded design: source bus has six sources plus an idle code, requiring ceil(log2 7)=3 bits. Destination group has four destinations plus no-write, requiring ceil(log2 5)=3 bits; this design intentionally permits at most one destination per microinstruction. ALU has eight choices requiring three bits. Memory command has idle/read/write requiring two bits. A 64-word control store needs a six-bit explicit next-address field. Four sequencing modes need two bits. Total width=3+3+3+2+6+2=19 bits. Store capacity=64×19=1216 bits=152 bytes of information, excluding implementation padding or ECC. Some encodings remain reserved.
A direct-control comparison gives one bit for each of six source enables, four destination enables, eight one-hot ALU selects and two memory enables: 20 action bits. Add the same six next-address and two sequencing bits: width 28; store 64×28=1792 bits=224 bytes. The controller must never assert conflicting bus drivers, multiple one-hot ALU choices or read/write simultaneously. Wider control does not make every bit combination legal.
5. Horizontal and encoded control trade-offs
Horizontal/direct controls expose more independent control choices and can express useful parallelism where the datapath allows it. Encoded/vertical fields can reduce width but require decoding and may restrict combinations. These are design tendencies, not proof that one is always faster or smaller overall: sequencer, decoder delay, datapath resources, microprogram length and storage organization also matter. A narrow word that needs more cycles may use more total control storage than expected.
Common mistakes
Draw available paths before optimizing a schedule. Track old/new values at edges. Separate architectural PC from micro-PC. Include idle choices in field cardinalities when required. Multiply control-word width by store depth; do not mistake address bits for word count. Count only documented padding/ECC.
Original practice: six single-correct MCQs
These original teaching questions are not previous-year questions. Choose exactly one answer.
P01. In the stated one-bus Y/ALU/Z datapath without bypass, minimum cycles for R3←R1+R2?
A. 1 B. 2 C. 3 D. 4
Answer: C
A: Operands and result cannot all traverse the single path in one cycle.
B: The newly latched Z cannot drive its new value earlier in the same cycle.
C: R1→Y; Y+R2→Z; Z→R3 needs three cycles.
D: Three suffice under the stated paths; a fourth is unnecessary.
P02. With one source bus and independently enabled destinations, which pair can share a cycle?
A. R1→Y and R2→MAR B. R1→Y and R1→MAR C. R1 drives bus and R2 drives bus D. New Z result drives bus before its latching edge
Answer: B
A: Two distinct source values need two drivers or another path.
B: One R1 bus value can be broadcast to two enabled destinations.
C: Simultaneous independent drivers conflict.
D: New Z is unavailable before its ending edge.
P03. A control field chooses one of eight source registers or no source. Minimum encoded width?
A. 3 bits B. 4 bits C. 8 bits D. 9 bits
Answer: B
A: Three bits cover eight choices, but nine are required including idle.
B: ceil(log2 9)=4 bits.
C: Eight resembles per-source enables, not minimum encoded width.
D: Nine is choice count, not binary width.
P04. A control store has 128 words of 40 bits. Raw capacity excluding padding/ECC?
A. 160 bytes B. 512 bytes C. 640 bytes D. 5120 bytes
Answer: C
A: This misses a factor of four in capacity.
B: This assumes 32-bit words instead of 40.
C: 128×40=5120 bits; /8=640 bytes.
D: 5120 is bits, not bytes.
P05. What does the micro-PC select?
A. Next program byte in ordinary instruction memory B. Current control-store microinstruction C. An arbitrary data-cache line D. Always the same address as the architectural PC
Answer: B
A: That is the architectural instruction-fetch PC’s role.
B: The micro-PC addresses control words that implement instructions.
C: Cache selection uses its own address mapping.
D: The two counters belong to different address spaces and purposes.
P06. A design has 3 source bits, 3 destination bits, 4 ALU bits, 2 memory bits, 7 next-address bits and 2 sequencing bits. Control-word width?
A. 14 bits B. 19 bits C. 21 bits D. 128 bits
Answer: C
A: This omits the seven next-address bits.
B: This omits the two sequencing bits.
C: 3+3+4+2+7+2=21 bits.
D: 128 is the number of addresses nameable by seven bits, not word width.
Sources and scope
Aligned to the 2026 course. This lesson covers the stated slice, not the entire COA syllabus. All numerical examples and questions are original. No claim of 2027 completeness.
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